(a) Field of the Invention
The present invention relates to a semiconductor device having a multi-wall cylindrical capacitor and, in particular, to the structure of a storage capacitor in a semiconductor device such as a semiconductor memory device generally referred to as a dynamic random access memory (DRAM). The present invention also relates to a method for manufacturing the same.
(b) Description of the Related Art
Recently, with the enhancement of the integration level in LSI, the chip area for the LSI decreases from year to year. With a DRAM, for example, in which a memory cell comprises a combination of a single transistor and a single capacitor, a reduction in the area of the capacitor used for a data storage element generally results in a reduced capacitance, which degrades the stability of the data storage by the capacitor. To prevent the reduction in the capacitance as a result of the reduction in the area of the capacitor, a variety of structures and their improvements are proposed for the capacitor which include a stacked structure inclusive of a cylinder type and a fin type and a trench structure as well as other structures.
FIGS. 1 to 4 show cross-sections of a capacitor of a cylindrical type in a conventional DRAM, at the consecutive steps of a method for manufacturing the same. In FIG. 1, a LOCOS film or field oxide film 12 is formed on a p-type silicon substrate 11 in a non-active region for separation of adjacent elements, followed by formation of a gate electrode 14 from a polycrystalline silicon (polysilicon) on an active region separated by the field oxide film 12, with a gate oxide film 13 interposed between the gate electrode 14 and the silicon substrate 11. An n-type impurity is doped into the surface region of the silicon substrate 11 on the opposite sides of the gate electrode 14, using the gate electrode 14 itself as a mask, to form an n.sup.- -type diffused regions 15 which serve as source/drain regions.
Subsequently, a first inter-layer dielectric film 16 is deposited on the entire surface of the p-type silicon substrate 11 inclusive of the gate electrode 14, followed by consecutive deposition of second and third interlayer dielectric films 17 and 18. The first to third interlayer dielectric films 16, 17 and 18 are selectively etched to form a contact-hole 19 for exposing one of the n.sup.- -type diffused regions 15, then a first blanket polysilicon layer 20 is deposited over the entire surface of the substrate 11 to fill the opening 19. Thereafter, as shown in FIG. 2, a relatively thick oxide film 21 made of, for example, BPSG (Boro-Phospho-Silicate Glass) is deposited which later defines a central core for the structure of a capacitor cylinder. Using a photolithographic technique, a photoresist pattern 22 is formed to cover a portion of the oxide film 21 located above the contact hole 19.
Thereafter, the oxide film 21 and polysilicon layer 20 are selectively etched by using the photoresist film 22 as a mask, followed by removal of the photoresist film 22, as shown in FIG. 3. Subsequently, a second blanket polysilicon film 23, which later defines an inner cylindrical portion of the storage electrode of the storage capacitor, and an oxide film 24 made of BPSG are consecutively deposited over the entire surface. Then, an etch-back of the oxide film 24 to define a sidewall insulator is effected, followed by deposition of a third blanket polysilicon layer 25 which later defines an outer cylindrical portion of the storage electrode.
An etch-back of the third and second polysilicon layer 25 and 23 is then effected to form a storage electrode having a double cylinder structure, as shown in FIG. 4. In this step, the BPSG film 24 provides a side-wall insulator for forming an outer cylindrical portion 25 of the storage electrode of the storage capacitor by self-alignment. Then, the exposed oxide film 21 and oxide film 24 are removed by using hot phosphoric acid, for example. Then, a Si.sub.3 N.sub.4 film, for example, is grown by a CVD process to form an insulating film 26c of the capacitor, followed by formation of a plate electrode 27 thereon. Finally, a fourth interlayer dielectric film 28 made of BPSG, for example, is deposited, followed by reflow thereof at 900.degree. C. in a N.sub.2 environment, for example.
In the semiconductor device as described above, a large step portion is formed on the interlayer dielectric film 28 at the boundary between the memory cell region having the storage capacitor and a peripheral circuit region. Even though the flatness of the interlayer dielectric film 28 can be improved to some degree by the reflow step as described above, it is difficult to substantially eliminate the step portion formed at the boundary. An angle (.theta.) of the step portion shown in FIG. 4 may be as high as 60.degree. or greater. This causes problems of a breakage in an overlying interconnection layer and of an etching residue remaining in the vicinity of the boundary due to the etching step to form the overlying interconnection layer.
In addition, since the conventional semiconductor device requires a reflow heat treatment at an elevated temperature to improve the flatness of the interlayer dielectric film, a substance having a low heat resistance such as Ta.sub.2 O.sub.5 cannot be suitably used as a material for the capacitor insulating film.